A First Generation DPGA Implementation

Article by Edward Tau, Ian Eslick, Derrick Chen, Jeremy Brown, and André DeHon published in Proceedings of the Third Canadian Workshop on Field-Programmable Devices (FPD'95, May, 1995), p. 138--143

Dynamically Programmable Gate Arrays (DPGAs) represent a hybrid architecture lying between traditional FPGAs and SIMD arrays. Notably, these arrays can efficiently support computations where the function of the array elements needs to vary both among array elements during any single cycle and within any single array element over time. We describe our minimal, first generation DPGA. This DPGA uses traditional 4-LUTs for the basic array element, but backs LUT and interconnect programming cells with a 4-context memory implemented using dynamic RAM. Additionally, this DPGA supports non-intrusive background loads of non-active contexts and automatic refresh for the dynamic memory cells. We draw several lessons from this design experience which may be relevant to future DPGA and FPGA designs.

Paper:

PDF dpga_proto_fpd95.pdf. [220KB]

Slides:

[PS slides]