Computer Science 294-7 Lecture #12
Interconnect

1.0 Interconnect

Some numbers from Lecture 4

The interconnect constitutes ~90% of the total area and 70-80% of the total delay.

In the reconfigurable domain, the interconnect has many issues to deal with

• there are thousands of operators producing results
• each if these operators should be able to take as input the results of the other operators
• the actual connections are not decided at fab time, they are late bound

For evaluating the different options let us assume that all of the operators have to be connected simultaneously.

1.1 Bisection Bandwidth

Bisection bandwidth = 2
Fig. 1.1

Bisection bandwidth = 1
Fig. 1.2

Bisection bandwidth = 3
Fig. 1.3

1.2 Interconnect Design Issues

• Flexibility

  Flexibility determines the ability to route anything within reason. For higher flexibility a higher bisection bandwidth and increased number of simultaneous routes are preferred.

• Area

  As far as the total area is concerned the bisection bandwidth should be smaller and the number of switches should be minimized.

• Delay

  From the delay perspective the total number of switches in path should be minimized along with the switch parasitics (stubs in path) and the wire length.

• Routability

  Routability is the difficulty of finding a route .

1.3 Attempt 1 - Crossbar

Fig. 1.4 Crossbar

1.3.1 Crossbar Analysis

Delay

Parasitic loads = kn
Switches/path = l
Wire length = O(kn)
Delay = O(kn)


Area

Bisection BW = n
Switches = $$kn²
Area = $$O(n²)

1.4 Attempt 2 - Mesh

• understand and exploit expected strucure
• locality - put connected components close together
• wires are expensive
• local connections cheaper than long ones

Fig. 1.5 Mesh Network

Fig. 1.6 Trying to place everything close

1.4.1 Mesh Analyis

Let l be the length of the wire, w the channel width, and n the number of LUTs.

Delay

Switches/path = l
Wire length = O(l)
Best Delay = O(w)
Worst Delay = $O(n½w)$


Area

Bisection BW = $wn½$
Switches = $O(nw2)$
Area = $O(nw2)$

• What is w?
• What can this route?
• Typical wire delay. Here you have to consider the fact that the switch delay is higher than that of the wire.

2.0 Rent's Rule

$IO\; =\; Cnp$

Consider an extreme case,

number of gates = n
inputs/gate = k
all the inputs of the gates arrive from the outside and the outputs go outside

C = k + 1 and p = 1 .

Fig. 2.1 Recursive Partitioning of circuit

Fig. 2.2 Rent's numbers for combinational logic

Random Logic



Specific Architectures

2.1 Caveats

• in modern "systems on a chip" the Rent's complexity parameters vary over the different sub-components
• the I/O at the natural boundaries are lesser
• at some level the system closes, eg. Workstation, PDA, etc.

  2.2 Wiring Requirements

  • $IO\; =\; O(np)$
    
  • $Side\; length\; at\; least\; =\; O(np)$
    
  • $Area\; at\; least\; =\; O(n2p)$
    
    • If wires are the limited resource, Area is $O(n2p)$
    • If wires are the limited resource, Area per LUT is $O(n2p-1)$, p > 0.5

  3.0 Switches

  Consider a specific structure built according to the Rent's rule.
  
  Fig. 3.1 Model hierarchical architecture
  This is a fully hierarchical interconnect with the following properties
  • inter-level signaling bandwidth growing according to Rent's rule
  • for simplicity only unidirectional signal wires are considered
  • gates recursively partitioned into n equally sized sets at each level of hierarchy
  • principal interconnect occurs at each node of convergence in the hierarchy
  • at any level l in the hierarchy, each node has a fan-in from below of $n\; x\; n$_outl-1 signals and a fan-in from above of $n$_inl
    
  From this the total number of switches can be calculated to give,
  further math (see thesis) gives,
  
  If switches are the limited resource,
  $Area\; per\; LUT\; =\; O(N$_LUT^2p-1) for p > 0.5
  Fig. 3.2 Switches and Wires, direct calculation
  
  Fig. 3.3 Switches and Wires, direct calculation
  (same as Fig. 3.2, but zoomed in to see p=0.5 better)
  

  4.0 Switches and Wires

  p < 0.5, Asymptotic Area per LUT is O(1)
  p > 0.5, Asymptotic Area per LUT is $O(n2p-1)$

  For p > 0.5 interconnect dominates. Note that the switching growth shown is the minimum required to route graphs for a given p.

  It is possible to construct architectures with BW and switching growth as shown to route any graph with $p$_graph <= p_net

  5.0 Shortcomings of Rent's Rule

  Eventhough Rent's rule estimates the number of wires and switches required to find a route, it is purely based on geometry, it does not consider the criical path. A partition can result in the critical path weaving between the halves. This is partly the reason why we see p~0.75 for high speed logic, while general logic has p~0.5.

  Fig. 5.1 illustrates this point. The left side is partitioned for minimum wires crossing halves. This results in the critcal path crossing the partition twice. In the figure on the right, the design has been reorganized to contain the critical path on one half, at the cost of a larger cut size between the halves.
  

  
  Fig. 5.1 Partitioning based on critical path length
  

  6.0 Efficiency

  Let, $p$_net is the designed net resource, and $p$_design is the number from Rent's rule.
  What happens when

  $p$_net> p_design?
  

  Wastage of routing resource.

  $p$_design> p_net?
  

  The LUTs have to be under-utilized by C so that routing is possible
  
  
  Figures below show the relative overheads for implementing $p$_design designs with $N$_LUT=4096 on $p$_net designs.
  Fig. 6.1 Efficiency - Discrete
  
  Fig. 6.2 Efficiency - Continuous
  Figure below plots the continuous case in three axes
  
  Fig. 6.3 Efficiency - Continuous
  The network connectivity can be picked if we assume the typical designs will have a uniform $p$_design. From this the expected overhead can be calculated. Figure below gives the expected overhead for $p$_design uniformly distributed between 0.4 <= $p$_design <=0.8.
  Fig. 6.4 Expected Overhead
  

  7.0 Sea of Gates

  Once the interconnect dominates and one expects a range of p's for subcomponents, focus on using the interconnect.
  
  Fig. 7.1 The Sea-of-Gates concept
  If most of the interconnect resources are usable as needed (not dedicated to a LUT), it does not hurt to have gates which you ignore when p is high.
  

  8.0 Summary

  • cannot afford full interconnect
  • cannot make all interconnects local
  • Rent's rule captures typical locality/structure in nets
  • Rent parameter varies among computing structures
  • interconnect resources grow as $O(n2p)$
  • too much interconnect can be just as inefficient as too little
  • demanding full routability of all designs hurts you in area
  • time for a Sea-of-gates philosophy for FPGAs ?

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  References

  1. B. S. Landman and R. L. Russo. On Pin Versus Block Relationship for Partitions of Logic Circuits. IEEE Transactions on Computers, 20:1469--1479, 1971. (n.b. This is the classic paper showing empirical evidence for Rent's Rule. You can scan it to get the key idea.)
  2. Abbas El Gamal. Two-Dimensional Stochastic Model for Interconnections in Master Slice Integrated Circuits. IEEE Transactions on Circuits and Systems, 28(2):127--138, February 1981. (n.b. The math gets a bit heavy. Reads this for the key results and don't sweat the more technical portions unless you really want.)
  3. W. R. Heller, C. George Hsi, Wadi F. Mikhaill. Wirability---Designing Wiring Space for Chips and Chip Packages. IEEE Design and Test of Computers, pages 43--51, August, 1984.
  4. André DeHon, Reconfigurable Architectures for General-Purpose Computing. AI Technical Report 1586, MIT Artificial Intelligence Laboratory, 545 Technology Sq., Cambridge, MA 02139, pages 63--88, October 1996. [PS for pp. 63-88], [HTML for Chapter 7], [Full Document].
  5. H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, pages 416-421. Addison Wesley Publishing Company, 1990.

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