Writings on Sublithographic/Molecular-Scale Architecture

• Crystals and Snowflakes: Building Computation from Nanowire Crossbars (IEEE Computer, 2011) -- general audience overview [Abstract and IEEE Xplore link]
• Nanowire-Based Programmable Architectures (ACM Journal on Emerging Technologies in Computing Systems, 2005) -- most comprehensive single article to date; this is the one article to read to get the current full story [Abstract and ACM Link]
• Seven Strategies for Tolerating Highly Defective Fabrication (IEEE Design and Test of Computers, 2005) -- how will we tolerate fabrication which leaves 1-10% of the wires broken and the junctions disconnected? [Abstract and IEEE Xplore Link]
• 3D Nanowire-Based Programmable Logic (Nanonets 2006) -- how to scale designs into three dimensions using multiple layers of nanowires [Abstract and Paper Links]
• Fault-Tolerant Sub-lithographic Design with Rollback Recovery (Nanotechnology, 2008) -- how to tolerate transient upsets during operation. [Abstract and IOP Link]
• Array-Based Architecture for FET-Based, Nanoscale Electronics (IEEE Tr. Nanotechnology, 2003) -- initial outline of how to build fully nanoscale programmable logic arrays using this technology [Abstract, Paper link]
• Stochastic Assembly of Sublithographic Nanoscale Interfaces (IEEE Tr. Nanotechnology, 2003) -- how to build decoders to bridge between lithographic and sublithographic scale, an important element of bootstrapping to programmability; also outlines nanoscale memory arrays [Abstract, Paper link]
• Radial Addressing of Nanowires (ACM Journal on Emerging Technologies in Computing Systems, 2006) -- a self-aligned technique for building nanoscale decoders to bridge between lithographic and sublithographic scales [Abstract and ACM Link]
• Law of Large Numbers System Design (Nano, Quantum and Molecular Computing: Implications to High Level Design and Validation) -- a more overview/tutorial article on coping with and exploiting statistical phenomena at the atomic scale [Abstract and Citation]
• Non-Photolithographic Nanoscale Memory Density Prospects (IEEE Tr. Nanotechnology, 2005) -- how to organize nanoscale memories and an assessment of the density they can provide with defect accounting [Abstract, Paper link ]
• Deterministic Addressing of Nanoscale Devices Assembled at Sublithographic Pitches (IEEE Tr. Nanotechnology, 2005) -- how to get deterministic addresses and multibit (word-wide) interfaces to stochastically assembled, nanoscale memories [Abstract, Paper link]
• Fault Secure Encoder and Decoder for NanoMemory Applications (IEEE Tr. VLSI Systems 2009) -- how to build the error-correction circuitry for memories in nanoscale logic and tolerate both defects and transient faults in the ECC logic [Abstract, Paper link]
• Inversion Schemes for Sublithographic Programmable Logic Arrays (IET CDT, 2009) -- how to use favorable pre-charge circuit configuration for nanoPLA evaluation (this is an improvement of the scheme in the JETC 2005 paper above) [Abstract and IEEE Xplore Link]
• VMATCH: Using Logical Variation to Counteract Physical Variation in Bottom-Up, Nanoscale Systems (ICFPT 2009) -- how to effectively map nanoPLA designs even if high variation in the nanoscale FETs make them ``inherently irreproducible'' [Abstract, Paper link]

Related

• Stochastic Spatial Routing for Reconfigurable Networks (Journal of Microprocessors and Microsystems, 2006) -- how to design devices for self routing [Abstract and DOI Link]
• Hardware-Assisted Simulated Annealing with Application for Fast FPGA Placement (FPGA 2003) -- how to do self placement [Abstract, Paper Link]
• Choose-Your-Own-Adventure Routing: Lightweight Load-Time Defect Avoidance (TRETS 2011) -- how to uses precomputed alternative routes to minimize the circuit complexity and time required to route around defects [Abstract, Paper Link]