Circuit-Level Modeling, Design, and Optimization for Digital Systems

Course: ESE370

Units: 1.0 CU
Terms: Fall
Next Offered: Fall 2013
When: MWF 12-1pm
Where: Towne 307
Instructor: DeHon (office Hour: T4:00pm-5:30pm)
TA: Spencer Lee (seas: lesp) (office hours: MW 4:55pm-5:55pm K-Lab)
Prerequisites: ESE170/171 (roundup of what you should know from ESE170)
ESE205/215 (roundup of what you should know from ESE215)
URL: <http://www.seas.upenn.edu/~ese370/>

Quick Links: [Course Objectives] [Grading] [Policies] [Fall 2013 Calendar] [Reading] [Piazza]

Catalog Level Description: Circuit-level design and modeling of gates, storage, and interconnect. Emphasis on understanding physical aspects which drive energy, delay, area, and noise in digital circuits. Impact of physical effects on design and achievable performance.

Role and Objectives

 The goal of this course is to teach students what they need to know about the physical aspects (area, delay, energy, noise) of electronic circuits to support high-speed, low-energy, area-efficient design of robust digital and computer systems. Students will learn: This course comes after a basic introduction to devices and circuits (ESE205/215) and a course on gate-level digital design (ESE170/171). It should serve both students who will go on to do circuit-level design and those who will work primarily at higher levels and need to be able to reason about technology and fundamental limits to establish capabilities and understand the circuit-level impact of optimizations they perform at higher levels of design. This will be the most detailed class on physical issues required for CMPE BSE students. Students may choose to continue with more advanced circuit and VLSI courses (e.g., ESE570).

Rough Syllabus (by weeks)

  1. Review transistor, introduce MOS model
  2. Gates and restoration, basic gate delay, review transient response
  3. MOS Transistors (models with physical device parameters (W,L,Na...)), scaling, variation
  4. Energy, Delay, Area implications and tradeoffs for MOS circuits
  5. Clocking, latches, flip-flops (setup, hold, clock skew)
  6. Other gate models (ratioed, pre/post-charge)
  7. RC Wire delay and Elmore delay (fanout, transistor sizing)
  8. Wire Effects (buffering, capacitive coupling/crosstalk)
  9. RAM design
  10. Noise: inductive coupling, ground bounce, ionizing particles, thermal noise
  11. Transmission lines
  12. High speed chip-to-chip signaling
  13. Energy and entropy

See Fall 2013 course calendar for day-by-day calendar with assignments.

Text

Grading

 Grading is based on weekly assignments and a longer end-of-term assignment. Projects: Two two-week design/optimization projects: (1) transistor design and optimization for logic/gates and (2) memory design.

Policies

Homework Turnin

Writeups must be done in electronic form and submitted through Canvas (next paragraph). Use CAD or drawing tools where appropriate. Use electric where required (for drawing up circuit diagrams). Use LaTex, Microsoft Word, or Google Docs for writeups (each provides an equation editor function, which you will need to use for writing up your equations).

Handwritten assignments and hand-drawn figures are not acceptable. Equations which are typed up but not formatted (such as through the Word equation editor or LaTex) are not acceptable. Unacceptable submissions will be automatically marked half off for each unacceptable entry. Illegible submissions will not be graded.

All assignments will be turned in electronically through the Penn Canvas website. Log in to canvas with your PennKey and password, then select ESE 370 from the Courses and Groups dropdown menu. Select Assignments from the links on the left and select the assignment you wish to submit for. Submissions should be as an archive (either .zip or .tar) and conform to the standards below.

The submitted archive must contain the following and be named <YourPennKey>_<HomeworkNumber>.<extension>

Late Assignments

Assignments must be turned in by the published due date to receive full credit. We deduct 10% of the assignment grade for each day late.

If assignments or exams fall due on a religious holiday, please make arrangements with the instructor to accommodate before the posted due date.

Use the Penn Course Absence Report (CAR) in Penn-in-Touch to report absences.

Credit Adjustment

Make sure you call any problems with grading to your TA's attention immediately and not later than the next class meeting after they are posted on blackboard. Our TA will be responsible for adjudicating these problems---the instructors will only be involved as a possible court of last appeal in case there is some truly difficult decision to make (i.e., in most cases, we will not be willing to second guess the TA's decisions). To submit a request to the TA for a review of a credit assignment on a lab assignment send an email to the TA stating the nature of the problem and the remedy you desire. We have instructed the TAs not to consider any requests for grade adjustments that are submitted later than the one week grace period after the grades are posted on blackboard. You are responsible for checking your posted grades in a timely manner.

Collaboration

You may help each other understand how to use the CETS computers and course CAD tools.

Each student is expected to do his/her own work -- including developing the details, drawing circuits, performing simulations, and writing the solutions. For the homeworks and projects, you are free to discuss basic strategies and approaches with your fellow classmates or others, but detail designs, implementations, analysis, and writeups should always be the work of the individual. If you get advice or insights from others that influenced your work in any way, please acknowledge this in your writeups.

In general, you are expected to abide by Penn's Code of Academic Integrity. If there is any uncertainty, please ask.

Previous Offerings

André DeHon