ESE370 Fall 2021 Working Schedule

Wk Lect. Date Lecture Slides Due Reading

1 1 9/1 W Intro/Overview [lec1] [lec1_6up] 1 through 1.2; review course web page completely

2 9/3 F Transistor Introduction (basics) and Gates from Transistors [lec2_pc] [lec2] [lec2_6up] review ESE215; 6.2 through static properties in 6.2.1

9/4 Sa Access Survey (in canvas)

2 9/6 M Labor Day

9/7 Tu Diagnostic Quiz (in Canvas)

9/8 W Lab 1 (Ketterer): Gate from Discrete Transistors Lab Data [Lab Instructions]

3 9/10 F Transistor Introduction (first order) [lec3_pc] [lec3] [lec3_6up] 3.1

3 4 9/13 M Regenerative Property [lec4_pc] [lec4] [lec4_ppt] 1.3.2

9/14 T HW 1 ADD DATE

5 9/15 W Delay and RC Response [lec5_pc] [lec5] [lec5_ppt] 1.3.3

6 9/17 F MOS Model [lec6_pc] [lec6] [lec6_ppt] 2.1-2.3, 3.3.1

4 7 9/20 M MOS Transistor Operating Regions: Part 1 [lec7_pc] [lec7] [lec7_ppt] HW 2, 22nm_HP.pm 3.3.2 (to pg 94)

8 9/22 W MOS Transistor Operating Regions: Part 2 [lec8_pc] [lec8] [lec8_ppt] 3.3.2 (to pg 103)

9 9/24 F MOS Transistor: Parasitics [lec9_pc] [lec9] [lec9_ppt] 3.3.2 (remainder)

5 10 9/27 M MOS Transistor Variation [lec10_pc] [lec10] [lec10_ppt] HW 3 3.3.3, 3.4

11 9/29 W Layout and Area [lec11_pc] [lec11] [lec11_ppt] 2.3

10/1 F Midterm 1: 7-9pm in Towne 309 (no lecture) exam (no answers) solutions

6 12 10/4 M MOS Scaling [lec12_pc] [lec12] [lec12_ppt] 3.5

13 10/6 W Performance: Inverter [lec13_pc] [lec13] [lec13_ppt] 5.4

14 10/8 F Performance: Gates [lec14_pc] [lec14] [lec14_ppt] HW 4 6.2.1 Delay and Performance (pp242-256)

7 15 10/11 M Energy Basics [lec15_pc] [lec15] [lec15_ppt] DROP DATE 5.5

16 10/13 W Energy and Delay Tradeoffs [lec16_pc] [lec16] [lec16_ppt] 6.2.1 Power Consumption (pp257-263)

10/15 F Fall Break HW 5

8 17 10/18 M Ratioed (Pseudo-nMOS) Logic [lec17_pc] [lec17] [lec17_ppt] 6.2.2

18 10/20 W Design Space Exploration [lec18_pc] [lec18] [lec18_ppt]

19 10/22 F Pass-Transistor Logic: Part 1 [lec19_pc] [lec19] [lec19_ppt] Proj 1.M 6.2.3

9 20 10/25 M Pass-Transistor Logic: Part 2 [lec20_pc] [lec20] [lec20_ppt] 6.2.3

21 10/27 W Distributed RC Wire Elmore Delay [lec21_pc] [lec21] [lec21_ppt] 4 to 4.3, 4.4, 4.5.1

22 10/29 F CMOS Worst Case Analysis and Logic Comparisons [lec22_pc] [lec22] [lec22_ppt] Proj 1 6.5

10 23 11/1 M Driving Large Capacitive Loads [lec23_pc] [lec23] [lec23_ppt] 5.4.3

11/3 W Midterm 2: 7-9pm in DRLB 3C2 (no lecture) exam (no answers) solutions

24 11/5 F Synchronous Timing Discipline and Clocking [lec24_pc] [lec24] [lec24_ppt] 7.1-7.3

11 25 11/8 M Dynamic Logic, Pt 1 [lec25_pc] [lec25] [lec25_ppt] Withdraw DATE 7.5

26 11/10 W Dynamic Logic, Pt 2 and Memory Overview [lec26_pc] [lec26] [lec26_ppt] 7.5, 12.1

27 11/12 F Memory Periphery and Serial Access Memories [lec27_pc] [lec27] [lec27_ppt] HW 6 12.2.3

12 28 11/15 M RAM Core Pt 1 [lec28_pc] [lec28] [lec28_ppt] 12.2.3

29 11/17 W RAM Core Pt 2 [lec29_pc] [lec29] [lec29_ppt] 12.3

30 11/19 F Inductive Noise [lec30_pc] [lec30] [lec30_ppt] 9.4.1, 4.3.3

13 11/22 M Lab 2 (Ketterer): Inductive Noise and Crosstalk [lab2] Proj 2.M

31 11/24 W ('F') Crosstalk [lec31_pc] [lec31] [lec31_ppt] 9.2.1

11/26 F Thanksgiving Holiday

14 11/29 M Lab 3 (Ketterer): Transmission Line Measurement [lab3]

32 12/1 W Transmission Line Intro and Analysis [lec32_pc] [lec32] [lec32_ppt] 4.4.5, 4.5.2, 9.4.2

33 12/3 F Trans. Line Modeling and Termination [lec33_pc] [lec33] [lec33_ppt] 4.4.5, 4.5.2, 9.4.2

12/5 Su Proj 2
15 34 12/6 M Transmission Lines Implications [lec34_pc] [lec34] [lec34_ppt]

35 12/8 W Repeaters in Wiring [lec35_pc] [lec35] [lec35_ppt] 9.3.3

36 12/10 F Course Summary [lec36]

12/12 Su HW 7

EW 12/17 F Final Exam 12-2pm in Moore 212 exam (no answers) solutions

Wk	Lect.	Date	Lecture	Slides	Due	Reading
1	1	9/1	W	Intro/Overview	[lec1] [lec1_6up]		1 through 1.2; review course web page completely
2	9/3	F	Transistor Introduction (basics) and Gates from Transistors	[lec2_pc] [lec2] [lec2_6up]		review ESE215; 6.2 through static properties in 6.2.1
	9/4	Sa			Access Survey (in canvas)
2		9/6	M	Labor Day
	9/7	Tu			Diagnostic Quiz (in Canvas)
	9/8	W	Lab 1 (Ketterer): Gate from Discrete Transistors	Lab Data		[Lab Instructions]
3	9/10	F	Transistor Introduction (first order)	[lec3_pc] [lec3] [lec3_6up]		3.1
3	4	9/13	M	Regenerative Property	[lec4_pc] [lec4] [lec4_ppt]		1.3.2
	9/14	T			HW 1 ADD DATE
5	9/15	W	Delay and RC Response	[lec5_pc] [lec5] [lec5_ppt]		1.3.3
6	9/17	F	MOS Model	[lec6_pc] [lec6] [lec6_ppt]		2.1-2.3, 3.3.1
4	7	9/20	M	MOS Transistor Operating Regions: Part 1	[lec7_pc] [lec7] [lec7_ppt]	HW 2, 22nm_HP.pm	3.3.2 (to pg 94)
8	9/22	W	MOS Transistor Operating Regions: Part 2	[lec8_pc] [lec8] [lec8_ppt]		3.3.2 (to pg 103)
9	9/24	F	MOS Transistor: Parasitics	[lec9_pc] [lec9] [lec9_ppt]		3.3.2 (remainder)
5	10	9/27	M	MOS Transistor Variation	[lec10_pc] [lec10] [lec10_ppt]	HW 3	3.3.3, 3.4
11	9/29	W	Layout and Area	[lec11_pc] [lec11] [lec11_ppt]		2.3
	10/1	F	Midterm 1: 7-9pm in Towne 309 (no lecture)	exam (no answers) solutions
6	12	10/4	M	MOS Scaling	[lec12_pc] [lec12] [lec12_ppt]		3.5
13	10/6	W	Performance: Inverter	[lec13_pc] [lec13] [lec13_ppt]		5.4
14	10/8	F	Performance: Gates	[lec14_pc] [lec14] [lec14_ppt]	HW 4	6.2.1 Delay and Performance (pp242-256)
7	15	10/11	M	Energy Basics	[lec15_pc] [lec15] [lec15_ppt]	DROP DATE	5.5
16	10/13	W	Energy and Delay Tradeoffs	[lec16_pc] [lec16] [lec16_ppt]		6.2.1 Power Consumption (pp257-263)
	10/15	F	Fall Break		HW 5
8	17	10/18	M	Ratioed (Pseudo-nMOS) Logic	[lec17_pc] [lec17] [lec17_ppt]		6.2.2
18	10/20	W	Design Space Exploration	[lec18_pc] [lec18] [lec18_ppt]
19	10/22	F	Pass-Transistor Logic: Part 1	[lec19_pc] [lec19] [lec19_ppt]	Proj 1.M	6.2.3
9	20	10/25	M	Pass-Transistor Logic: Part 2	[lec20_pc] [lec20] [lec20_ppt]		6.2.3
21	10/27	W	Distributed RC Wire Elmore Delay	[lec21_pc] [lec21] [lec21_ppt]		4 to 4.3, 4.4, 4.5.1
22	10/29	F	CMOS Worst Case Analysis and Logic Comparisons	[lec22_pc] [lec22] [lec22_ppt]	Proj 1	6.5
10	23	11/1	M	Driving Large Capacitive Loads	[lec23_pc] [lec23] [lec23_ppt]		5.4.3
	11/3	W	Midterm 2: 7-9pm in DRLB 3C2 (no lecture)	exam (no answers) solutions
24	11/5	F	Synchronous Timing Discipline and Clocking	[lec24_pc] [lec24] [lec24_ppt]		7.1-7.3
11	25	11/8	M	Dynamic Logic, Pt 1	[lec25_pc] [lec25] [lec25_ppt]	Withdraw DATE	7.5
26	11/10	W	Dynamic Logic, Pt 2 and Memory Overview	[lec26_pc] [lec26] [lec26_ppt]		7.5, 12.1
27	11/12	F	Memory Periphery and Serial Access Memories	[lec27_pc] [lec27] [lec27_ppt]	HW 6	12.2.3
12	28	11/15	M	RAM Core Pt 1	[lec28_pc] [lec28] [lec28_ppt]		12.2.3
29	11/17	W	RAM Core Pt 2	[lec29_pc] [lec29] [lec29_ppt]		12.3
30	11/19	F	Inductive Noise	[lec30_pc] [lec30] [lec30_ppt]		9.4.1, 4.3.3
13		11/22	M	Lab 2 (Ketterer): Inductive Noise and Crosstalk	[lab2]	Proj 2.M
31	11/24	W ('F')	Crosstalk	[lec31_pc] [lec31] [lec31_ppt]		9.2.1
	11/26	F	Thanksgiving Holiday
14		11/29	M	Lab 3 (Ketterer): Transmission Line Measurement	[lab3]
32	12/1	W	Transmission Line Intro and Analysis	[lec32_pc] [lec32] [lec32_ppt]		4.4.5, 4.5.2, 9.4.2
33	12/3	F	Trans. Line Modeling and Termination	[lec33_pc] [lec33] [lec33_ppt]		4.4.5, 4.5.2, 9.4.2
	12/5	Su			Proj 2
15	34	12/6	M	Transmission Lines Implications	[lec34_pc] [lec34] [lec34_ppt]
35	12/8	W	Repeaters in Wiring	[lec35_pc] [lec35] [lec35_ppt]		9.3.3
36	12/10	F	Course Summary	[lec36]
	12/12	Su			HW 7
EW		12/17	F	Final Exam 12-2pm in Moore 212	exam (no answers) solutions

This working calendar is on the web: http://www.seas.upenn.edu/~ese370/fall2021/syllabus.html. Please, recheck the page on the web as details may be adjusted as the term progresses. Lectures notes, reading, and handouts will be filled as we reach them.

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