Reading

• Day 1
  • Recommended:
    1. Stephen M. Trimberger. Three Ages of FPGAs: A Retrospective on the First Thirty Years of FPGA Technology. In Proceedings of the IEEE, Volume 103, Number 3, p. 318--331, March 2015.
    2. Louise H. Crockett, Ross A. Elliot, Martin A. Enderwitz, and Robert W. Stewart. Chapters 1, 2, 6, In Zynq Book.
  • Supplemental:
    1. Xilinx UltraScale+ MPSoC Zynq Overview
    2. Mark Bohr, A 30 Year Retrospective on Dennard's MOSFET Scaling Paper, In IEEE Solid-State Circuits Society Newsletter, 12(1):11--13, Winter, 2007.
    3. Robert H. Dennard, Fritz H. Gaensslen, Hwa-Nien Yu, V. Leo Rideout, Ernest Bassous, and Andre R. LeBlanc. Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions. Journal of Solid-State Circuits, 9(5):256--268, October 1974. (also reprinted on p. 38 of the SSCS Newsletter above)
       
    4. Nachiket Kapre and André DeHon. SPICE²: Spatial Processors Interconnected for Concurrent Execution for Accelerating the SPICE Circuit Simulator Using an FPGA. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 31, Number 1, pp. 9--12, DOI: 10.1109/TCAD.2011.2173199, January, 2012. [Abstract and Paper Link]
• Day 2
  • Recommended:
    1. Wikipedia Article on Amdahl's Law
    2. Donald E. Knuth. An empirical study of FORTRAN programs. In Software Practice and Experience, Volume 1, Number 2, pages 105--133, August, 1971. See Canvas site.
  • Supplemental:
    1. Gene Amdahl. Validity of the single processor approach to achieving large scale computing capabilities. In Proceedings of the Spring Joint Computer Conference (AFIPS), Pages 483-485, 1967. This is the original article, but it's not the most tutorial read.
    2. Mark D. Hill and Michael R. Marty. Amdahl's Law in the Multicore Era. In IEEE Computer, Volume 41, Number 7, Pages 33--38, July 2008.
• Day 3
  • Recommended:
    1. Ulrich Drepper, What Every Programmer Should Know about the Memory, 2007 Chapters 1--3.2
  • Supplemental:
    1. Brent Keeth and Jacob Baker, DRAM Circuit Design: A Tutorial, IEEE Press, 2001, pp. 108--116.
    2. Ashok K. Sharma, Semiconductor Memories, IEEE Press, 1997, pp. 230--248.
• Day 4
  • Recommended:
    1. André DeHon. Chapter 5, In Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation, Elsevier, 2008. See Canvas site.
  • Supplemental:
    1. C. A. R. Hoare. Communicating Sequential Processes, In Communications of the ACM, Volume 21, Number 8, pp. 666--677, August 1978.
• Day 5
  • Recommended:
    1. Gilles Kahn. The Semantics of a Simple Language for Parallel Processing. In Information Processing, pages 471--475, 1974.
  • Supplemental:
    1. Edward A. Lee and David G. Messerschmitt. Synchronous Data Flow. In Proceedings of the IEEE, Volume 75, Number 9, pp. 1235--1245, September, 1987.
    2. André DeHon, Yury Markovsky, Eylon Caspi, Michael Chu, Randy Huang, Stylianos Perissakis, Laura Pozzi, Joseph Yeh, and John Wawrzynek. Stream Computations Organized for Reconfigurable Execution, In Microprocessors and Microsystems, Volume 30, Number 6, Pages 334--354, September 2006. See Canvas site.
    3. Edward A. Lee. and Albert Sangiovanni-Vincintelli. A Framework for Comparing Models of Computation. In IEEE Transactions on Computer-Aided Design, Volume 17, Number 12, pp. 1217--1229, December, 1998.
• Day 6
  • Recommended:
    1. W. Daniel Hillis and Guy L. Steele Data Parallel Algorithms. In CACM 29(12)1170--1183, 1986.
    2. John Wawrzynek, Krste Asanovic, Brian Kingsbury, David Johnson, James Beck, and Nelson Morgan. Spert-II: A Vector Microprocessor System, IEEE Computer, 1996.
  • Supplemental:
    1. R.M. Russell, The CRAY-1 Computer System. In CACM 21(31)63--72, 1978.
• Day 7
  • Recommended:
    1. Greg Snider, Performance-Constrained Pipelining of Software Loops onto Reconfigurable Hardware, FPGA, 2002.
       Note: Background section is most relevant for this day; the rest may be a bit early, but becomes more relevant over the next few lectures.
  • Supplemental:
    1. TBD
• Day 8
  • Recommended:
    1. André DeHon. The Density Advantage of Configurable Computing. IEEE Computer, 33(4):41--49, April 2000.
    2. Ryan Kastner, Janarbek Matai, and Stephen Neuendorffer. Chapter 1.2. In Parallel Programming for FPGAs
  • Supplemental:
    1. Timothy J. Callahan, John R. Hauser and John Wawrzynek The GARP Architecture and C Compiler. IEEE Computer, vol. 33, no. 4, pp. 62-69, Apr 2000.
• Day 9
  • Recommended:
    1. Timothy J. Callahan and André DeHon. Chapter 7. In Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation, Elsevier, 2008. See Canvas site.
    2. Louise H. Crockett, Ross A. Elliot, Martin A. Enderwitz, and Robert W. Stewart. Chapters 14, 15, In Zynq Book.
  • Supplemental:
    1. HLSynth TRCAD 2011
• Day 10
  • Recommended:
    1. UG1393: Vitis Unified Software Platform Documentation Application Acceleration Development Chapter 4 and 7.
    2. UltraFast High-Level Productivity Design Methodology Guide (UG1197) most of Chapter 4, C-based IP-development, p. 35--57.
  • Supplemental:
    1. Ryan Kastner, Janarbek Matai, and Stephen Neuendorffer. Parallel Programming for FPGAs
    2. Vivado Design Suite Users Guide: High Level Synthesis (UG902), Optimizing the Design, pp. 131--187. (some overlap with above, so read above and skim redundant sections.)
    3. Zhipeng Zhao and James C. Hoe. Using Vivado-HLS for Structural Design: a NoC Case Study, CMU 2017.
• Day 11
  • Recommended:
    1. Haiqian Yu and Miriam Leeser. Automatic Sliding Window Operation Optimization for FPGA-Based Computing Boards. In Proceedings of the International Symposium on Field-Programmable Custom Computing Machines, pp. 76--88, 2006.
    2. Louise H. Crockett, Ross A. Elliot, Martin A. Enderwitz, and Robert W. Stewart. Chapter 9.3, 10 In Zynq Book.
  • Supplemental:
    1. Louise H. Crockett, Ross A. Elliot, Martin A. Enderwitz, and Robert W. Stewart. Chapter 19 In Zynq Book.
    2. Eric S. Chung, James C. Hoe and Ken Mai. CoRAM: an in-fabric memory architecture for FPGA-based computing, in Proceedings of the International Symposium on Field-Programmable Gate Arrays, pp. 97--106, 2011.
    3. Andrew S. Huang and John P. Shen. ``A Limit Study of Local Memory Requirements Using Value Reuse Profiles'', in Proceedings of MICRO-28, pp. 71--81, December, 1995.
    4. Edward A. Lee. The Problem with Threads. In IEEE Computer, Volume 39, Issue 5, pp. 33--42, 2006.
• Day 13
  • Recommended:
    1. UG1393: Vitis Unified Software Platform Documentation Application Acceleration Development Chapters 3, 5, 6, and 7.
       Last half of 7 is more related to Day 11; useful reference if you need more details.
  • Supplemental:
    1. TBD
• Day 14
  • Recommended:
    1. Ryan Kastner, Janarbek Matai, and Stephen Neuendorffer. Chapter 9. In Parallel Programming for FPGAs
    2. Ulrich Drepper, What Every Programmer Should Know about the Memory, 2007 Chapters 1--3.2
  • Supplemental:
    1. TBD
• Day 15
  • Recommended:
    1. Frederick P. Books. ``The Mythical Man-Month after 20 Years'', in The Mythical Man Month Essays on Software Engineering Anniversary Eddition, Addison Wesley, pp. 267--268, 1995.
  • Supplemental:
    1. Beginner Git Tutorial with background
    2. Basic Git Tutorial (goes a bit further, less background)
    3. git cheat sheet
• Day 16
  • Recommended:
    1. See project handout.
  • Supplemental:
    1. TBD
• Day 17
  • Recommended:
    1. Udit Dhawan and André DeHon. Area-Efficient Near-Associative Memories on FPGAs. In ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 7, Number 4, DOI: 10.1145/2629471, January, 2015.
  • Supplemental:
    1. Adam Kirsch and Michael Mitzenmacher. 2010. The power of one move: Hashing schemes for hardware. IEEE/ACM Trans. Networking 18, 6 (2010), 1752--1765.
• Day 19
  • Recommended:
    1. Matteo Frigo and Steven G. Johnson, The Design and Implementation of FFTW3. In Proceedings of the IEEE, vol. 93, no. 2, pp. 216--231, 2005. (This focusses on the design space.)
  • Supplemental:
    1. Steven W. Smith, The Scientist and Engineer's Guide to Digital Signal Processing, (This is for background on the Fourier Transform and FFT. Chapter 12 is FFT. May want to go back to Chapter 8 for DFT introduction.)
    2. Ryan Kastner, Janarbek Matai, and Stephen Neuendorffer. Chapter 4 and 5. In Parallel Programming for FPGAs (This looks specifically at writing FFTs in C for HLS.)
    3. R. Clint Whaley, Antoine Petitet, and Jack Dongarra. Automated Empirical Optimization of Software and the ATLAS Project. In Parallel Computing, Volume 27, pp. 3--35, February, 2001. (This is automated desgin-space exploration for matrix multiplication.)
• Day 20
  • Recommended:
    1. Brian Baley. Verification Introduction blog post, 2011.
    2. Brian Baley. Directed and Random Testing blog post, 2011.
  • Supplemental:
    1. GNU Test Coverage (gcov): Introduction
    2. Koen Claessen and John Hughes. QuickCheck: a lightweight tool for random testing of Haskell programs, ICFP 2000.
       [a QuickCheck for C] [a lightweight QuickCheck for C]
    3. K. Datta and P.P. Das. Assertion based verification using HDVL, Proceedings of the International Conference on VLSI Design, 2004.
       (has SystemVerilog asserting examples)
    4. Osman Balci. Principles and techniques of simulation validation, verification, and testing. Proceedings of the onference on Winter simulation, 1995.
    5. A. Aharon, A. Bar-David, B. Dorfman, E. Gofman, M. Leibowitz, and V. Schwartzburd. Verification of the IBM RISC System/6000 by a Dynamic Biased Pseudo-Random Test Program Generator, IBM System Journal, Vol. 30, No. 4, 1991.
    6. A. Adir, E. Almog, L. Fournier, E. Marcus, M. Rimon, M. Vinov, and A. Ziv. Genesys-Pro: innovations in test program generation for functional processor verification, IEEE Design and Test of Computers, Vol. 21, No. 2, 2004.
• Day 21
  • Recommended:
    1. TBD
  • Supplemental:
    1. S. Devadas, H-K. T. Ma., and A. R. Newton. On the verification of sequential machines at differing levels of abstraction, IEEE Transactions on Computer-Aided Design of Integrated Circuits, Volume 7, Number 6, pp. 713--722, 1988.
    2. E. M. Clarke, E. A. Emerson, and A. P. Sistia. Automatic verification of finite-state concurrent systems using temporal logic specifications, ACM Transactions on Programming Languages and Systems, Volume 8, Number 2, pp. 244--263, 1986.
• Day 22
  • Recommended:
    1. F. Thomson Leighton. Introduction to Parallel Algorithms and Architectures: Arrays, Trees, Hypercubes, 1992, Morgan-Kaufmann. pp. 32--42. See Canvas site for excerpts.
  • Supplemental:
    1. J. Sklansky, Conditional-Sum Addition Logic. IRE Transactions of Electronic Computers, EC-9:226--231, June, 1960.
    2. Richard P. Brent and H. T. Kung, A Regular Layout for Parallel Adders. In IEEE Transactions on Computers, 31(3):260--264, March 1982.
    3. Karl Papadantonakis, Nachiket Kapre, Stephanie Chan, and André DeHon. Pipelining Saturated Accumulation. In IEEE Transactions on Computers, Volume 58, Number 2, pp. 208--219, February, 2009.
    4. Nachiket Kapre and André DeHon. Optimistic Parallelization of Floating-Point Accumulation. In Proceedings of the IEEE Symposium on Computer Arithmetic (ARITH18), pp. 205--213, June 2007.
    5. Vipula Sateesh, Connor Mkckeon, Jared Winograd, and André DeHon. Pipelined Parallel Finite Automata Evaluation. In Proceedings of the IEEE International Conference on Field-Programmable Technology, December, 2019.
• Day 23
  • Recommended:
    1. Joseph A. Fisher. Very Long Instruction Word Architectures and the ELI-512. In Proceedings of the International Symposium on Computer Architecture, 1983.
    2. Ilian Tili, Kalin Ovtcharov, and J. Gregory Steffan. Reducing the Performance Gap between Soft Scalar CPUs and Custom Hardware with TILT. In ACM Transactions on Reconfigurable Technology and Systems, Vol. 10, No. 3., July 2017, Article No. 22.
  • Supplemental:
    1. Joseph A. Fisher. ``Retrospective: Very Long Instruction Word Architectures and the ELI-512,'' In 25 Years of the International Symposia on Computer Architecture: Selected Papers, pp. 34--36, 1998.
    2. PICO (Program In, Chip Out): Automatically Designing Custom Computers. In IEEE Computer, vol. 35, no. 9, pp. 39-47, September 2002.
• Day 24
  • Recommended:
    1. Monica Lam. Software Pipelining: An Effective Scheduling Technique for VLIW Machines. In Proceedings of the ACM SIGPLAN 1988 Conference on Programming Language Design and Implementation, pp. 318--328, 1988.
  • Supplemental:
    1. TBD
• (orphaned)
  • Recommended:
    1. TBD
  • Supplemental:
    1. B. S. Landman and R. L. Russo. On Pin Versus Block Relationship for Partitions of Logic Circuits. IEEE Transactions on Computers, 20(12):1469--1479, 1971. (n.b. This is the classic paper showing empirical evidence for Rent's Rule.)
    2. Naveen Muralimanohar, Rajeev Balasubramonian, and Norman P. Jouppi. CACTI 6.0: A Tool to Model Large Caches. HPL-2009-85, HP Labs, Palo Alto, CA, 2009.
    3. Special issue of IEEE Solid-State Circuits Magazine on Rent, including original memo
• (orphaned)
  • Recommended:
    1. Edin Kadric, David Lakata, André DeHon, Impact of Parallelism and Memory Architecture on FPGA Communication Energy. In ACM Trans. on Reconfigurable Technology and Systems, 2016.
  • Supplemental:
    1. Rajesh Kumar and K. Bernstein. Scaling, power, and the future of CMOS. In Technical Digest of the IEEE International Electron Device Meeting, December 2005, pp. 7--15.
    2. Hadi Esmaeilzadeh, Emily Blem, Rene St. Amant, Karthikeyan Sankaralingam, and Doug Burger Dark silicon and the end of multicore scaling'' in Proceedings of the International Symposium on Computer Architecture, 2011, pp. 365--376.
    3. Borivoje Nikolic. Design in the Power-limited Scaling Regime. In IEEE Transaction on Electron Devices, Volume 55, Number 1, pp. 71--83, 2008.
    4. David J. Frank. ``Power-constrained CMOS Scaling Limits,'' IBM Journal of Research and Development, Volume 46, Number 2/3, March/May, 2002. See Canvas site.
    5. S. Hanson, B. Zhai, K. Bernstein, D. Blaauw, A. Bryant, L. Chang, K. K. Das, W. Haensch, E. J. Nowak, and D. M. Sylvester. ``Ultralow-voltage, minimum-energy CMOS,'' IBM Journal of Research and Development, Volume 50, Number 4/5, pp. 471--490, July/September 2006.
    6. David Bol, Renaud Ambroise, Denis Flandre, and Jean-Didier Legat. ``Interests and Limitations of Technology Scaling for Subthreshold Logic,'' In IEEE Trans. on VLSI Systems, Vol. 17, No. 10, pp. 1508--1519, 2009.
    7. Anantha P. Chandrakasan, Samuel Sheng, and Robert W. Brodersen, ``Low-Power CMOS Digital Design,'' in IEEE Journal of Solid State Circuits, 1992, Vol. 27, No. 4, pp. 473--484.
    8. Richard P. Feynman. Feynman Lectures on Computation. Westview Press, 1999. Chapter 5: Reversible Computation and the Thermodynamics of Computation, pp. 137--184.
• Day 25
  • Recommended:
    1. Ben Lickly, Isaac Liu, Sungjun Kim, Hiren Patel, Stephen A. Edwards, and Edward A. Lee. Predictable programming on a precision timed architecture, In Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES), pp. 137--146, 2008.
  • Supplemental:
    1. TBD
• Extra (Day 25 extended)
  • Recommended:
    1. Robert Walker and Samit Chaudhuri. Introduction to the Scheduling Problem, IEEE Design and Test of Computers, Volume 12, Issue 2, pp. 60--69, 1995.
  • Supplemental:
    1. The Synchronous Data Flow Pogramming Language LUSTRE. In Proceedings of the IEEE, 1991.
    2. The Synchronous Approach to Reactive and Real-Time Systems. In Proceedings of the IEEE, 1991.