http://www.seas.upenn.edu/~ese535/spring2015/spring2015.html for updates.
| Date | Topic | Slides | Reading | ||
|---|---|---|---|---|---|
| 1/14 | Introduction, Motivation, Overview | pptx, pdf | Fundamental Reconfig | ||
| 1/19 | MLK Holiday (no class) | ||||
| 1/21 | Heterogeneous Multi-Context Architecture | pptx, pdf | Absolute Energy FPGA2014 | ||
| 1/22 | Assign P1 Due | ||||
| 1/26 | Covering | pptx, pdf | Devadas p190--198 | ||
| 1/28 | Partitioning I (formulation and KLFM) | pptx, pdf | KLFM DAC 1982 | ||
| 1/29 | Assign P2 Due | ||||
| 2/2 | Clustering | pptx, pdf | flowmap TRCAD 1994 | ||
| 2/4 | Partitioning II (spectral, maxflow, replication) | pptx, pdf | Hall Mngmt Sci 1970 | ||
| 2/5 | Assign P3 Due | ||||
| 2/9 | Scheduled Operator Sharing | pptx, pdf | HL Synth D&T 1994 | ||
| 2/11 | Scheduling I (formulation, List Scheduling) | pptx, pdf | Scheduling Intro D&T 1995 | ||
| 2/12 | Assign P4 Due with exercise | ||||
| 2/16 | Scheduling II (force-directed, Branch-and-Bound) | pptx, pdf | Scheduling Intro D&T 1995 (cont.) | ||
| 2/18 | Architecture Synthesis | pptx, pdf | PICO Computer2002 | ||
| 2/19 | Assign P5 Due with exercise | ||||
| 2/20 | Drop Day | ||||
| 2/23 | FPGA (no class) | ||||
| 2/25 | Placement I (formulation and constructive) | pptx, pdf | Part Place ISPD 1997 | ||
| 2/26 | Assign P6 Due | ||||
| 3/2 | Placement II (simulated annealing) | pptx, pdf | SA Science 1983 | ||
| 3/4 | Routing I (variants, formulation, channel routing, over-the-cell) | pptx, pdf | Left Edge DAC 1971 | ||
| 3/5 | Assign P6 Accepted | ||||
| 3/9 | Spring Break (no class) | ||||
| 3/11 | Spring Break (no class) | ||||
| 3/16 | Routing II (Pathfinder congestion negotiation, FPGA routing) | pptx, pdf | Pathfinder FPGA 1995 | ||
| 3/18 | (no class; no midterm) | ||||
| 3/19 | Assign P7 Due | ||||
| 3/23 | Dataflow Compute Models | pptx, pdf | SDF Proc. IEEE 1987 | ||
| 3/25 | High-level Synthesis I (C-to-dataflow graph) | pptx, pdf | Hauck+DeHon, Ch. 7 | ||
| 3/19 | Assign P8 Due | ||||
| 3/27 | Withdraw Day | ||||
| 3/30 | High-level Synthesis II: Dataflow Subgraph Sharing | pptx, pdf | HLSynth
TRCAD 2011
Pattern FPGA2008 |
||
| 4/1 | Satisfiability (SAT) solvers | pptx, pdf | Chaff DAC2001 | ||
| 4/2 | Project Proposal Due | 4/6 | Two-level Logic | pptx, pdf | Devadas p59--91 |
| 4/8 | FSM Encoding (Sequential logic) | pptx, pdf | Exact Encode TRCAD 1991 | ||
| 4/9 | Milestone 1 Due | ||||
| 4/13 | FSM Equivalence Checking | pptx, pdf | seq. verify TRCAD 1988 | ||
| 4/15 | Multi-level Logic | pptx, pdf | Devadas p151--184 | ||
| 4/16 | Milestone 2 Due | ||||
| 4/20 | Static Timing Analysis | pptx, pdf | Devadas p225--256 | ||
| 4/22 | Statistical Static Timing Analysis | pptx, pdf | SSTA DAC 2002 | ||
| 4/23 | Milestone 3 Due | ||||
| 4/27 | Retiming | pptx, pdf | Retime Caltech VLSI 1983 | ||
| 4/29 | Processor Verification | pptx, pdf | Processor Verify CAV 1994 | ||
| 4/29 | Project Report Due | ||||