Nhlanhla Mavuso

Pioneering High-Performance Computing Architectures

About Me

As an accelerated Master's student in Electrical Engineering at the University of Pennsylvania and an undergraduate pursuing Physics and Computer Engineering, my passion lies in pushing the boundaries of computing performance through innovative hardware solutions. My research and projects are centered around FPGA-based hardware acceleration and high-performance computing architectures, with a focus on applications in data analytics and beyond Moore's Law scaling limitations.

With 2+ years of hands-on experience, I specialize in FPGA design, digital simulation, and timing analysis, complemented by strong skills in C/C++, Python, and hardware description languages (SystemVerilog, Verilog, HLS). My work in the Implementation of Computation Lab has focused on enhancing FPGA resilience and performance through techniques like real-time reconfiguration and high-resolution timing measurement.

Beyond research, I bring an entrepreneurial drive to translate technological advancements into real-world impact, as demonstrated through my early-stage startup, Cortex Forge, exploring FPGA-based AI acceleration. I am eager to contribute to cutting-edge research and collaborate with leading experts to solve complex challenges in computing.

Education

Experience

Cortex Forge - Founder & CEO (Feb 2025 – Present)
  • Early stage startup (currently operating in stealth mode) founded by a group of Computer Engineers at the University of Pennsylvania that develop FPGA processing engines (accelerators) for energy intensive and resource intensive tasks not limited to (Gene sequencing, and alignment).
Research Assistant, System Architecture Integration Lab, University of Pennsylvania (Sep 2024 – Feb 2025)
  • Developed a Python-based machine learning model for server QoS compliance prediction in datacenter configurations, utilizing data engineering, feature engineering, and model evaluation.
  • Implemented data loading, feature engineering (scaling, one-hot encoding), and model training (Random Forest, Decision Tree), achieving high performance metrics.
  • Evaluated model performance using accuracy, precision, recall, F1-score, and ROC curves.
Undergraduate Researcher, Implementation of Computation Lab, University of Pennsylvania (May 2023 – Present)
  • FPGA Timing & Resilience: Developed intra-CLB reconfiguration for real-time FPGA link repair, enhancing critical path timing by 10% on a 100MHz clock and achieving sub-5-second in-system reconfiguration.
  • High-Resolution Timing Measurement: Implemented online timing measurement on Xilinx Artix-7 FPGA, achieving resolution of 11.2ps - 17.9ps at 1GHz - 1.6GHz VCO frequencies.
  • FPGA Vulnerability Analysis: Investigated process variation, aging, and environmental impacts on FPGAs, quantifying up to 190ps timing overhead, informing resilience strategies.
Teaching Assistant, ESE 3500: Embedded Systems, University of Pennsylvania (Spring 2025)
  • Led labs and lectures for 50 students on embedded systems design principles, fostering hands-on project-based learning and mentoring in baremetal C firmware development.
  • Designed course assessments and held weekly office hours to reinforce key concepts in embedded systems.

Projects

Technical Skills

Contact

Email: nmavusocorner@gmail.com

GitHub: GitHub Profile

LinkedIn: LinkedIn Profile