We'll now create a Verilog description of the inverter.
Note: you may run into errors if your Verilog cell and module name shares a name with a Verilog primitive (i.e., nand, nor, not,...). It is recommended to make the cell name for these simple gates to be something like "my_nand", "nand_xyz" (substitute your initials for xyz) - so that the netlister does not think you are trying to redefine any logic primitives.
In your library manager click once on the ESE570 library and then click once on the inv cell view. Now left click Library manager:File->New Cellview. In the dialog box type functional in the View Name field. Select Verilog-Editor for the Tool. Make sure that you inv is selected in the Cell category and ESE570 is selected in the Library field.
Left click OK. The text tool should now appear, with some basic template stuff inside. Anything preceded by a "//" is considered to be a comment.
After a while (it might take about quite a while), an Emacs editor window will pop up. You need to prepend the following lines to it:
`resetall
`celldefine
`delay_mode_path
`timescale 1ns/10ps
Then append the following to the same functional view:
`endcelldefine
Make sure you use the backtick character ( ` ) rather than a single quote ( ' ) in the above lines. The backtick character shares its key with the tilde (~) and is located on the upper left corner of most keyboards, right below Esc.
Next, add the following the statement in between the module statements:
not (out, inp);
If the input and output names are not “in” and “out” for you, substitute them with your own names. The (out, in) syntax specifies the output and input for the inverter. In Verilog, the convention is that the output arguments of the module (gate) are listed before going on to the inputs.
This is all the text you need in order to describe your inverter. Now you can save the text file and close it. Cadence will tell you in the CIW whether the functional view is successfully parsed (no syntax errors) or not.
Now you are ready to simulate your Verilog code.
The commands that you used in the text file are describe bellow.
module - defines the beginning of a Verilog module.
inv(...) - Specifies the name of the module. All pins (connections to the outside world) must be specified inside the parenthesis.
in/out - Defines what the input/output pins into the module are.
not - tells that this gate is an inverter. There are three basic gates AND, OR, NOT, NAND, and NOR.
endmodule - signifies the end of this particular module.
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