8/28
8/30

Introduction (slides, pptx)
Early machines (slides, pptx)

9/4
9/6

Microcoding (slides, pptx)
CISC to RISC (slides, pptx)

9/11

9/13

Homework #1 Due,
Paper Discussion #1
Pipelining I (slides, pptx)

9/18
9/20

Pipelining II (slides, pptx)
Instruction-level parallelism I (slides, pptx)

9/25
9/27

Instruction-level parallelism II (slides, pptx)
Instruction-level parallelism III (slides, pptx),
Homework #2 Due

10/4
10/6

Paper discussion II [papers]
Midterm exam

10/9
10/11

Memory I (slides, pptx)
Memory II (slides, pptx)

10/16
10/18

Fall break
Virtual Memory (slides, pptx)

10/19

Homework #3 Due
Project Proposal Due

23 Oct
25 Oct

Paper discussion III [papers]
VLIW (slides, pptx)

30 Oct
1 Nov

Multi-threading (slides, pptx)
Vectors (slides, pptx)

6 Nov
8 Nov

Multiprocessors (slides, pptx)
Paper discussion IV

13 Nov

15 Nov

Advanced topics -- technology
Homework #4 Due
Advanced topics -- specialization

20 Nov
22 Nov

Summary (slides, pptx)
Thanksgiving

27 Nov
29 Nov

Paper discussion V [papers]
No class

7 Dec

Project Report Due

12 Dec

Final Exam

Papers I

• Hill et al. "Classic machines: Technology, implementation, and economics"
• Moore. "Cramming more components onto integrated circuits"
• Radin. "The 801 minicomputer"
• Patterson et al. "The case for the Reduced Instruction Set Computer"
• Colwell et al. "Instruction sets and beyond: Computers, complexity, controversy"

Papers II

• Srinivasan et al. "Optimizing pipelines for power and performance"
• Mahlke et al. "A Comparison of Full and Partial Predicated Execution Support for ILP Processors"
• Palacharla et al. "Complexity-Effective Superscalar Processors"
• Yeh et al. "Two-Level Adaptive Training Branch Prediction"

Papers III

• Jouppi. "Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers"
• Kim et al. "An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches"
• Fromm et al. "The energy efficiency of IRAM architectures"
• Lee et al. "Phase change memory architecture and the quest for scalability"

Papers IV

• Mudge, "Power: A first-class architectural design constraint"
• Lamport. "How to make a multiprocessor computer that correctly executes multiprocess programs"
• Lenoski et al. "The Stanford DASH Multiprocessor"
• Tullsen et al. "Simultaneous multithreading: Maximizing on-chip parallelism"

Papers V

• Horowitz et al. "Scaling, power, and the future of CMOS"
• Reddi et al. "Web search using mobile cores: Quantifying and mitigating the price of efficiency"
• Dally et al. "Efficient Embedded Computing"