30 Aug
1 Sep

Introduction (slides, pptx)
Early machines (slides, pptx)

6 Sep
8 Sep

Microcoding (slides, pptx)
CISC to RISC (slides, pptx), Homework #1 Due

13 Sep
15 Sep

Paper discussion I (slides, pptx), Paper Discussion #1
Pipelining I (slides, pptx)

20 Sep
22 Sep

Pipelining II (slides, pptx)
Instruction-level parallelism I (slides, pptx)

27 Sep
29 Sep

Instruction-level parallelism II (slides, pptx)
Instruction-level parallelism III (slides, pptx), Homework #2 Due

4 Oct
6 Oct

Paper discussion II (slides, pptx) [papers]
Midterm exam

11 Oct
13 Oct

Fall break
Memory I (slides, pptx)

18 Oct
20 Oct

Memory II (slides, pptx)
Virtual memory (slides, pptx)

25 Oct
27 Oct

Paper discussion III [papers], Homework #3 Due
VLIW (slides, pptx)

1 Nov
3 Nov

Multi-threading (slides, pptx)
Vectors (slides, pptx)

8 Nov
10 Nov

Multiprocessors (slides, pptx)
Paper discussion IV [papers]

15 Nov
17 Nov

Advanced topics -- technology, Homework #4 Due
Advanced topics -- specialization

22 Nov
24 Nov

Advanced topics -- datacenters
Thanksgiving

29 Nov
1 Dec

Paper discussion V [papers]
Summary (slides, pptx)

Paper Discussion I

• Hill et al. "Classic machines: Technology, implementation, and economics"
• Moore. "Cramming more components onto integrated circuits"
• Radin. "The 801 minicomputer"
• Patterson et al. "The case for the Reduced Instruction Set Computer"
• Colwell et al. "Instruction sets and beyond: Computers, complexity, controversy"

Paper Discussion II

• Srinivasan et al. "Optimizing pipelines for power and performance"
• Mahlke et al. "A Comparison of Full and Partial Predicated Execution Support for ILP Processors"
• Palacharla et al. "Complexity-Effective Superscalar Processors"
• Yeh et al. "Two-Level Adaptive Training Branch Prediction"

Paper Discussion III

• Jouppi. "Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers"
• Kim et al. "An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches"
• Fromm et al. "The energy efficiency of IRAM architectures"
• Lee et al. "Phase change memory architecture and the quest for scalability"

Paper Discussion IV

• Mudge, "Power: A first-class architectural design constraint"
• Lamport. "How to make a multiprocessor computer that correctly executes multiprocess programs"
• Lenoski et al. "The Stanford DASH Multiprocessor"
• Tullsen et al. "Simultaneous multithreading: Maximizing on-chip parallelism"

Paper Discussion V

• Horowitz et al. "Scaling, power, and the future of CMOS"
• Reddi et al. "Web search using mobile cores: Quantifying and mitigating the price of efficiency"
• Dally et al. "Efficient Embedded Computing"